In many electronic circuit applications, data signals from one device need to be delivered to another device. For example, data signals from a particular chip in an application-specific integrated circuit (ASIC) may be delivered via appropriate interconnects to another chip in the same ASIC. In order to reduce the number of inter-chip interconnects required in such an application, it is not uncommon for a set of data lines from one chip to be at least partially serialized before being delivered over the interconnects to the other chip. The function is performed by a circuit known as a serializer.
In operation, a serializer in the first chip takes a set of output data lines, e.g., a set of 16 data lines, and generates an output requiring a reduced set of data lines, e.g., a set of four data lines, by at least partially serializing the data, e.g., converting the output data from a 16-line parallel arrangement to a 4-line parallel arrangement. A corresponding deserializer in the second chip receives the serialized data, and converts it back to its original parallel format. A first chip clock signal is also typically delivered from the first chip to the second chip for use in the deserialization process. The data may then be processed in the parallel format in the second chip, using a clock signal associated with the second chip.
A problem that arises in the above-described serialization and deserialization process is that, although the clock signals of the first and second chips typically have the same frequency, the phase relationship between these clock signals is usually unknown, i.e., the clock signals are asynchronous. This can lead to other significant problems, such as violation of minimum setup and hold times in the second chip, or metastability. It is therefore generally necessary to synchronize the deserialized data stream with a known clock signal phase, such that the deserialized stream can be properly processed in the second chip. One approach to providing this synchronization is a clock recovery technique in which the data is used as an input to a phase-locked loop (PLL) which recovers an appropriately-timed system clock. Unfortunately, this approach may not be suitable for applications in which a large number of synchronous clocks need to be provided in the second chip.
Another synchronization approach involves oversampling the incoming data with multiphase clocks from a PLL. However, this approach is also unsuitable for use in certain applications, in that it typically requires a custom PLL which may not be desirable to include in the chip. Yet another conventional approach is that described in P. Plaza et al., “A 2.5 Gb/s ATM Switch Chip Set,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 3, pp. 405-415, September 1996, which eliminates the phase difference by asynchronously writing each of the output data lines from the deserializer to a corresponding FIFO buffer, and then reading out the data using a common system clock. The drawbacks of this approach are that it generally introduces a significant amount of latency, and may also significantly increase circuit cost and complexity.
A need therefore exists for improved signal procesing techniques suitable for use in applications involving the transfer of data between asynchronously-clocked chips or other types of circuits, devices and systems.